Power Supply with Integrated PassivEs.The EU FP7 PowerSwipe Project

Autor: Mathúna, C. Ó, Wang, N., Kulkarni, S., Anthony, R., Nicolas Cordero, Oliver, J., Alou, P., Svikovic, V., Cobos, J. A., Cortés, J., Neveu, F., Martin, C., Allard, B., Voiron, F., Knott, B., Sandner, C., Maderbacher, G., Pichler, J., Agostinelli, M., Anca, A., Breig, M.
Přispěvatelé: Centro de Electrónica Industrial, Universidad Politécnica de Madrid (UPM), Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), IPDiA, European Project: 318529,EC:FP7:ICT,FP7-ICT-2011-8,POWERSWIPE(2012), Ampère, Publications, POWER SoC With Integrated PassivEs - POWERSWIPE - - EC:FP7:ICT2012-10-01 - 2016-03-31 - 318529 - VALID
Jazyk: angličtina
Rok vydání: 2014
Předmět:
Zdroj: Proceedings of the 8th International Conference on Integrated Power Electronics Systems
8th CIPS
8th CIPS, Feb 2014, Nuremberg, Germany. pp.278-284
Scopus-Elsevier
Popis: International audience; Combining high efficiency with cost-effective but high level of integration is a major driver in power electronics today. The EU FP7 PowerSwipe consortium proposes to develop next generation Power Supply in Package (PwrSiP) and Power Supply on Chip (PwrSoC) technology platforms through innovations in integrated power passives, nanoCMOS technologies and advanced packaging. This work focusses on the development of a full supplychain for integrated power management technology including the first integrated system-level design tool for System on Chip (SoC) applications; high-volume MEMS manufacturing processes for monolithic power passives and 3D, embedded, wafer-level packaging technology to achieve a highly integrated SoC solution for automotive applications.
Databáze: OpenAIRE