PFS - Tools for the Analysis of Simulation Dumps and the Evaluation of Burn-In Techniques

Autor:	Calabrese, Andrea
Jazyk:	angličtina
Rok vydání:	2022
Předmět:	Microelectronics Spinitronics parallel algorithms Automotive Integrated circuits Microelectrònica Burn-in test Circuits integrats Espintrònica EDA operating system-level optimizations Enginyeria electrònica::Microelectrònica [Àrees temàtiques de la UPC]
Zdroj:	UPCommons. Portal del coneixement obert de la UPC Universitat Politècnica de Catalunya (UPC)
Popis:	While the importance of parallel hardware architectures has been increasing over the decades, software tends to be one step behind. In the testing and reliability field, noncommercial software is often designed with few to no parallelism in mind. In this paper, we focus on a toolchain that allows us to measure the stress metrics of large SoC through the analysis of enormous Value Change Dump files produced by the testing and simulation equipment. In this toolchain, we concentrate on speeding up the analysis and making the entire process more automatic through pipeline and parallelization techniques. We tested the resulting Burn-In test application on a real chip, developed by STMicroelectronics.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::de7d03bd3b179eb551f8612dd2044608 https://hdl.handle.net/2117/369972 Zobrazit plný text záznamu