Modeling of Real Bistables in VHDL
| Autor: | Acosta Jiménez, Antonio José, Barriga Barros, Ángel, Valencia Barrero, Manuel, Bellido Díaz, Manuel Jesús, Huertas Díaz, José Luis |
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| Přispěvatelé: | Universidad de Sevilla. Departamento de Tecnología Electrónica |
| Jazyk: | angličtina |
| Rok vydání: | 1993 |
| Předmět: | |
| Zdroj: | idUS. Depósito de Investigación de la Universidad de Sevilla instname |
| Popis: | A complete VHDL model of bistables including their metastable operation is presented. An RS-NAND latch has been modelled as a basic structure, orienting its implementation towards its inclusion in a cell library. Two applications are included: description of a more complex latch (D-type) and description of a circuit containing three latches where metastable signals are propagated. Simulation results show that the presented niodel provides very realistic information about the device behavior, which until now had to be obtained through electric simulation. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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