Unified evaluation model for interconnection schemes used in behavioral synthesis
| Autor: | Cesario, W., Kission, P., GUILLAUME, Ph., Jerraya, Ahmed |
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| Přispěvatelé: | Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Torella, Lucie |
| Jazyk: | francouzština |
| Rok vydání: | 1997 |
| Předmět: | |
| Zdroj: | International Workshop on Logic and Architecture Synthesis (IWLAS'97) International Workshop on Logic and Architecture Synthesis (IWLAS'97), Dec 1997, Grenoble, France |
| Popis: | International audience; This paper introduces a new methodology to evaluate datapath interconnection schemes at the behavioral level. This evaluation model is validated by comparison with RTL synthesis evaluation results. It has been implemented and used for architecture exploration in order to select the best interconnection scheme to use. A generic datapath model capable of representing a variety of interconnection schemes is presented. The efficiency of each scheme depends on the application under synthesis. In general, mux-based interconnections are more efficient for resources with low sharing factors. Contrarily, designs that employs a large controller or a large instruction set to enable high resource sharing factors give better results with bus-based interconnections. Experiments have shown that comparison using a behavioral level evaluation model is enough for quality measurement and qualitative classification. |
| Databáze: | OpenAIRE |
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