Matlab based environment for designing DSP systems using IP blocks
| Autor: | Zergainoh, Nacer-Eddine, Jerraya, Ahmed, Popovici, K., Urard, P. |
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| Přispěvatelé: | Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), STMicroelectronics [Crolles] (ST-CROLLES), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), Torella, Lucie |
| Jazyk: | angličtina |
| Rok vydání: | 2004 |
| Předmět: | |
| Zdroj: | Proceedings of 12th Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI'04) The 12th Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI'04) The 12th Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI'04), Oct 2004, Kanazawa, Japan. pp.296-302 |
| Popis: | International audience; In this paper, we propose an efficient IP block based design environment for high throughput VLSI Systems. The flow generates SystemC Register Transfer Level (RTL) architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. This experimentations show that the approach can produce efficient RTL architecture and allow for huge saving of time. |
| Databáze: | OpenAIRE |
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