THESIC : Una plataforma flexible para la validation funcional de circuitos integrados
| Autor: | Velazco, R., Rezgui, S., Reguer, E. |
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| Přispěvatelé: | Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Torella, Lucie, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS) |
| Jazyk: | francouzština |
| Rok vydání: | 2001 |
| Předmět: | |
| Zdroj: | IBERCHIP IBERCHIP, Mar 2001, Montevideo, Uruguay |
| Popis: | International audience; This work aims at describing the main features of a system, the so-called THESIC tester, devoted to the functional validation of integrated circuits. This system, initially designed to set-up radiation test experiments of digital architectures, is composed of two main blocs: a motherboard for the interface with the user and the control of the circuit under test operation and a daughter board in which is implemented a suitable architecture around the circuit to be tested. The THESIC version presented in this paper was enhanced in order to significantly simplify the daughter board developments, whose architecture is implemented through an FPGA programming |
| Databáze: | OpenAIRE |
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