An Experimental Comparative Study of Fault-Tolerant Architectures
| Autor: | Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard |
|---|---|
| Přispěvatelé: | Conception et Test de Systèmes MICroélectroniques (SysMIC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Lebrun, Caroline |
| Jazyk: | angličtina |
| Rok vydání: | 2015 |
| Předmět: | |
| Zdroj: | 7th International Conference on Advances in System Testing and Validation Lifecycle VALID: Advances in System Testing and Validation Lifecycle VALID: Advances in System Testing and Validation Lifecycle, Nov 2015, Barcelone, Spain. pp.1-6 HAL |
| Popis: | International audience; This paper provides a comparative study based on experiments performed on four similar fault-tolerant architectures intended to reduce errors caused due to faults in combinational logic parts of microelectronic circuits and systems. The compared merits include area, power, performance and fault tolerance capability. The experimental results show that the improved Hybrid Fault-Tolerant Architecture can handle transient faults as effectively as Partial-TMR and exhibits permanent fault tolerance capability similar to that of Full-TMR. It offers 11.8% and 20.5% power saving compared to Partial and Full-TMR respectively. Furthermore, it can handle the fault accumulation effect better than TMR, hence an ideal candidate for low-power long duration mission-critical applications. |
| Databáze: | OpenAIRE |
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