A new frequency synthesizer stabilization method based on a mixed phase locked loop and delay locked loop
| Autor: | Lucas de Peslouan, Pierre-Olivier, Majek, Cédric, Taris, Thierry, Deval, Yann, Begueret, Jean-Baptiste, Belot, Didier |
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| Přispěvatelé: | Laboratoire de l'intégration, du matériau au système (IMS), Centre National de la Recherche Scientifique (CNRS)-Institut Polytechnique de Bordeaux-Université Sciences et Technologies - Bordeaux 1, STMicroelectronics [Crolles] (ST-CROLLES) |
| Jazyk: | angličtina |
| Rok vydání: | 2011 |
| Předmět: | |
| Zdroj: | A new frequency synthesizer stabilization method based on a mixed phase locked loop and delay locked loop IEEE International Symposium on Circuits and Systems (ISCAS) IEEE International Symposium on Circuits and Systems (ISCAS), May 2011, Rio de Janeiro, Brazil. pp.82-89 |
| Popis: | International audience; A novel technique for the stabilization of local oscillators is presented in this paper based on the combination of a Phase Locked Loop (PLL) and a Delay Locked Loop (DLL) architecture. On one hand, phase noise performances are improved taking advantage of both architectures and in particular to the non-accumulation of random timing jitter in DLL mode. On the other hand, the settling time (less than 0.5µs) of the system is optimized by the increase of the PLL bandwidth, up to instable mode. Multistandard synthesis is so performed within a 1 - 5 GHz range, with a swift agility from one to one. |
| Databáze: | OpenAIRE |
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