Design of the circuit blocks for successive approximation register analog to digital converter in 0.35 um CMOS technology
| Autor: | Miletić, Tomislav |
|---|---|
| Přispěvatelé: | Koričić, Marko |
| Jazyk: | chorvatština |
| Rok vydání: | 2014 |
| Předmět: |
CMOS sklopka
CMOS transmission gate TEHNIČKE ZNANOSTI. Računarstvo TEHNIČKE ZNANOSTI. Elektrotehnika S&H sklop pretpojačalo bistabil komparator kontrolna logika D/A pretvornik S&H circuit control logic preamplifier TECHNICAL SCIENCES. Electrical Engineering TECHNICAL SCIENCES. Computing latch comparator D/A converter |
| Popis: | U ovom radu projektirani su sklopovski blokovi SAR A/D pretvornika korištenjem 0.35 µm CMOS tehnologije. Za postizanje željenih specifikacija analizirana je konfiguracija S&H sklopa s mogućnosti poništavanja napona pomaka pojačala. U S&H sklopu korištene su CMOS sklopke. Komparator je projektiran u konfiguraciji pretpojačala i bistabila radi postizanja vrlo brzog odziva. Kontrolna logika koja se sastoji od kružnog brojila i posmačnog registra ostvarena je asinkronim D bistabilima. Nadalje, projektirani D/A pretvornik s raspodijeljenim nabojem sadrži kapacitivnu mrežu i ugrađeni S&H sklop. Blokovi su projektirani za tipičan tehnološki proces i radne uvjete na razini električke sheme. Postignute su karakteristike koje zadovoljavaju primjenu u SAR ADP-u razlučivosti 12 bita i frekvencije uzorkovanja 1 MS/s. In this thesis the circuit blocks of an SAR A/D converter were designed in 0.35 µm CMOS technology. To achieve the target specifications, a configuration of an S&H circuit with the cancellation of amplifier offset voltage was analysed. CMOS transmission gates were used in the S&H circuit. The comparator was designed in a configuration of a preamplifier and a latch, in order to achieve a very short response time. The control logic consisting of ring counter and shift register was realised using asynchronous D-type flip-flops. Moreover, designed charge redistribution D/A converter has capacitive network and inherent S&H circuit. The Blocks were designed for typical process corners on the schematic level. The required performance for the application in a 12-bit 1 MS/s SAR ADC was achieved. |
| Databáze: | OpenAIRE |
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