Discrete-continuous semantic adaptations for simulating SysML models in VHDL-AMS
| Autor: | Daniel Café, Hardebolle, C., Jacquet, C., Dos Santos, F. V., Boulanger, F. |
|---|---|
| Přispěvatelé: | Chaire Conception Analogique Avancée Thales/Supélec, Thales Communications [Colombes], THALES-THALES-Supélec Sciences des Systèmes (E3S), Ecole Supérieure d'Electricité - SUPELEC (FRANCE)-Ecole Supérieure d'Electricité - SUPELEC (FRANCE), Supélec Sciences des Systèmes (E3S), Ecole Supérieure d'Electricité - SUPELEC (FRANCE), Daniel Balasubramanian, Christophe Jacquet, Pieter Van Gorp, Sahar Kokaly, Tamás Mészáros |
| Předmět: | |
| Zdroj: | Scopus-Elsevier Proceedings of the 8th Workshop on Multi-Paradigm Modeling MPM 2014 MPM 2014, Daniel Balasubramanian; Christophe Jacquet; Pieter Van Gorp; Sahar Kokaly; Tamás Mészáros, Sep 2014, Valencia, Spain. pp.11-20 |
| Popis: | International audience; Our research focuses on the simulation of heterogeneous systems modeled in SysML, in particular, systems that mix different engineering domains such as mechanics, analog and digital circuits. Because of their nature, expressing multi-paradigm behavior in heterogeneous systems is a cumbersome endeavor. SysML does not provide a standard method for defining the operational semantics of individual blocks nor any intrinsic adaptation mechanism when coupling blocks of different domains. We present in this paper a way to address these obstacles. We give well-defined operational semantics to SysML blocks by using profile extensions, together with a language for the description of adaptors. We apply our approach to a test case, using a toolset for SysML to VHDL-AMS transformation, capable of automated generation of VHDL-AMS code for system verification by simulation. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|