Performance evaluation methods for MPSoC Design
| Autor: | Jerraya, A.A., Bacivarov, I. |
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| Přispěvatelé: | Torella, Lucie, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA) |
| Jazyk: | angličtina |
| Rok vydání: | 2006 |
| Předmět: | |
| Zdroj: | EDA for IC System Design, Verification, and Testing EDA for IC System Design, Verification, and Testing, CRC Press, Chapter 6, 2006, Series: Electronic Design Automation for Integrated Circuits Hdbk |
| Popis: | ISBN: 0849379237; Multi-processor systems-on-chip (MPSoCs) require the integration of heterogeneous components (e.g., micro-processors, DSP, ASIC, memories, buses, etc.) on a single chip. The design of MPSoC architectures requires the exploration of a huge space of architectural parameters for each component. The challenge of building high-performance MPSoCs is closely related to the availability of fast and accurate performance evaluation methodologies. This chapter provides an overview of the performance evaluation methods developed for specific subsystems. It then proposes to combine subsystem performance evaluation methods to deal with MPSoC. |
| Databáze: | OpenAIRE |
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