Ultrafast safety system to turn-off normally on SiC JFETs
| Autor: | Dubois, Fabien, Bergogne, Dominique, Risaletto, Damien, Perrin, Rémi, Zaoui, Abderrahime, Morel, Hervé, Meuret, Régis |
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| Přispěvatelé: | Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), SAFRAN, Grp Hispano Suiza, SAFRAN Group |
| Jazyk: | angličtina |
| Rok vydání: | 2011 |
| Předmět: | |
| Zdroj: | Proceedings of the IEEE 14th European Conference on Power Electronics and Applications EPE EPE, Aug 2011, Birmingham, United Kingdom. pp.CD |
| Popis: | International audience; The use of normally on Silicon Carbide (SiC) JFET devices poses the question of safety and reliability in Voltage Fed Inverter (VFI) applications. Indeed, when a JFET is not driven with a sufficient negative voltage, the JFET is conducting and the VFI may be short-circuited. Therefore, it is needed to generate a negative voltage to turn-off the JFET to protect the VFI in case of gate driver failure. The settling time of this negative voltage must be inferior to the power system constant time to reduce the rise time of the short-circuit current. In this paper, a solution to protect the JFET and the system is proposed. A circuit description of an innovative topology using a Forward-Flyback topology with Primary Side Sensing (PSS) technique and an Output Voltage Estimation based on the Time Constant Matching (OVETCM) is presented. Moreover, the converter protects the VFI for an input range from 3 V to 610 V and up to 150 °C. Experimental results are provided and validate the design of the safety system. |
| Databáze: | OpenAIRE |
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