Analysis and optimization of a debug post-silicon hardware architecture
| Autor: | Sanchez Moreno, Joel |
|---|---|
| Přispěvatelé: | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Espasa Sans, Roger, Izquierdo Ustrell, Miquel |
| Jazyk: | angličtina |
| Rok vydání: | 2022 |
| Předmět: |
Depuració (Informàtica)
Esperanto Technologies ET-SoC-1 Arquitectura d'ordinadors Debug Debugging in computer science Disseny de Processadors Architecture Computer architecture SoC Processor Design Post-silicon Validation Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC] Arquitectura |
| Zdroj: | UPCommons. Portal del coneixement obert de la UPC Universitat Politècnica de Catalunya (UPC) |
| Popis: | The goal of this thesis is to analyze the post-silicon validation hardware infrastructure implemented on multicore systems taking as an example Esperanto Technologies SoC, which has thousands of RISC-V processors and targets specific software applications. Then, based on the conclusions of the analysis, the project proposes a new post-silicon debug architecture that can fit on any System on-Chip without depending on its target application or complexity and that optimizes the options available on the market for multicore systems. |
| Databáze: | OpenAIRE |
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