MODEST: a model for energy estimation under spatio-temporal variability
| Autor: | Ganapathy, Shrikanth, Canal Corretger, Ramon, González Colás, Antonio María, Rubio Sola, Jose Antonio |
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| Přispěvatelé: | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica, Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors, Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
| Jazyk: | angličtina |
| Rok vydání: | 2010 |
| Předmět: |
Hardware_MEMORYSTRUCTURES
Circuits integrats -- Disseny i construcció Cache memory Memòria ràpida de treball (Informàtica) Spatio-temporal variability Memòria cau DSM scaling Enginyeria electrònica::Microelectrònica::Circuits integrats [Àrees temàtiques de la UPC] Cache Design Integrated circuits -- Design and construction |
| Zdroj: | UPCommons. Portal del coneixement obert de la UPC Universitat Politècnica de Catalunya (UPC) Recercat. Dipósit de la Recerca de Catalunya instname |
| Popis: | Estimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of the changing operating and environmental conditions which makes the problem of energy estimation more dynamic in nature. It is worsened by process induced variations of low level parameters like threshold voltage and channel length. In this paper we present MODEST, a proposal for estimating the static and dynamic energy of caches taking into account spatial variations of physical parameters, temporal changes of supply voltage and environmental factors like temperature. It can be used to estimate the energy of different blocks of a cache based on a combination empirical data and analytical equations. The observed maximum and median error between MODEST and HSPICE energy-estimates for 22,500 samples is around 7.8% and 0.5% respectively. As a case study, using MODEST, we propose a two step iterative optimization procedure involving Dual-Vth assignment and standby supply voltage minimization for reclaiming energy-constrained caches. The observed energy reduction is around 50.8% for the most-leaky Cache. A speed-up of 750X over conventional hard-coded implementation for such optimizations is achieved. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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