Timing Closure Management based on Delay Bound Determination
| Autor: | Azemard, Nadine, Aline, Michel, Maurine, Philippe, Auvergne, Daniel |
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| Přispěvatelé: | Conception et Test de Systèmes MICroélectroniques (SysMIC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM) |
| Jazyk: | angličtina |
| Rok vydání: | 2001 |
| Předmět: | |
| Zdroj: | IFIP International Conference on Very Large Scale Integration-The Global System On Chip Design & CAD Conference VLSI-SoC: Very Large Scale Integration-System-on-Chip VLSI-SoC: Very Large Scale Integration-System-on-Chip, Dec 2001, Montpellier, France. pp.430-434 |
| Popis: | International audience; In this paper we present a method to determine the feasibility of delay constraint imposed on circuit path. This is of prime importance in minimizing the number of iterations when satisfying performance constraints in IC design. From a layout oriented study of the path delay distribution, we show how to obtain the upper and lower bounds of the delay of combinational paths. Then we characterize these bounds and present a method to determine, on the path under study, the average weighted loading factor which allows to satisfy the delay constraint. Example of application is given on different ISCAS circuits. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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