A 2.5ns-Latency 0.39pJ/b 289µm2/Gb/s Ultra-Light-Weight PRINCE Cryptographic Processor
| Autor: | Miura, Noriyuki, Matsuda, Kohei, Myszkowski, Karol, Nagata, Makoto, Bhasin, Shivam, Yli-Mayry, Ville, Homma, Naofumi, Mathieu, Yves, Graba, Tarik, Danger, Jean-Luc |
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| Přispěvatelé: | Secure and Safe Hardware (SSH), Laboratoire Traitement et Communication de l'Information (LTCI), Institut Mines-Télécom [Paris] (IMT)-Télécom Paris-Institut Mines-Télécom [Paris] (IMT)-Télécom Paris, Département Communications & Electronique (COMELEC), Télécom ParisTech, HAL, TelecomParis |
| Jazyk: | angličtina |
| Rok vydání: | 2017 |
| Předmět: | |
| Zdroj: | Symposium on VLSI Circuits Symposium on VLSI Circuits, Jun 2017, Kyoto, Japan. pp.C266-C267 |
| Popis: | An ultra-light-weight PRINCE cryptographic processor is developed. A fully-unrolled differential-logic architecture saves delay, energy, and area (i.e. hardware weight) of XOR as a dominant cipher component. An S-box is composed only by four kinds of compact composite gates and a replica-delay-based transition-edge aligner prevents glitches accumulated in the long unrolled combinational- logic data path to further suppress the weight. A 28nm CMOS prototype successfully demonstrates 2.5ns-latency with 0.39pJ/b and 289µm 2 /Gb/s of ultra-light-weight cryptographic performance. |
| Databáze: | OpenAIRE |
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