VES3 - Testing and Analyzing Throughout the Silicon Lifecycle
| Autor: | Ruiz, Robert, Allen, Ramsay |
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| Jazyk: | angličtina |
| Rok vydání: | 2022 |
| Předmět: | |
| Zdroj: | UPCommons. Portal del coneixement obert de la UPC Universitat Politècnica de Catalunya (UPC) |
| Popis: | The time required for testing silicon defects continues to rise as design complexity and transistor count increases in-line with Moore’s Law. Structured test, particularly scan compression, assists with reducing the amount of time and effort involved. Furthermore, the associated design-for-test (DFT) is often reusable for determining the root cause of defective silicon behavior. However, new challenges associated with higher system integration, such as 3D-IC and chiplet packaging technologies, and shrinking time-to-market, requires a new approach to achieve low defect levels and gain understanding of defective or abnormal behavior This relatively new approach is known as Silicon Lifecycle Management (SLM) and enables testing and analysis throughout the different silicon life phases, and utilized analytics (diagnostics) to improve each phase from design to in-field operation. This presentation covers a discussion on SLM that is built on in-chip environmental, structural, and functional monitors and can leverage DFT hardware to enable deep insights from silicon die to assembled systems. We discuss the similarities to a structured manufacturing test flow such as implementation, data acquisition from the silicon, analytics on the data, and corresponding corrective action. Additionally, key differences are pointed out, especially regarding real-time or in-situ operational requirements. Data is gathered at every opportunity during the device lifecycle providing continuous analysis and actionable feedback. With respect to test methods such as stored manufacturing test patterns or built-in-self test, SLM extends the ability to test beyond die and package phases, enabling testing silicon throughout its life cycle. |
| Databáze: | OpenAIRE |
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