| Autor: |
Park, Juhun, Park, Jaehyun, Park, Jejune, Hwang, Kyuman, Yun, Jinchan, Kim, Dahye, Park, Sungil, Yang, Jinwook, Jeong, Jae Won, Yun, Chuljin, Bae, Jinho, Huh, Daihong, Yeon, Deukho, Kim, Sanghyeon, Baek, Seungeun, Son, Soomin, Lee, Junghan, Kim, Tae-Sun, Lee, Seungjun, Lee, Sun-Jung, Park, Sang Wuk, Kuh, Bong Jin, Ha, Daewon, Hyun, Sangjin, Ahn, Su Jin, Song, Jaihyuk |
| Zdroj: |
Japanese Journal of Applied Physics; December 2024, Vol. 63 Issue: 12 p120803-120803, 1p |
| Abstrakt: |
Beyond MBCFETTMtechnology, the 3-dimensional stacked FET (3DSFET) emerges as a promising contender, featuring a structure that stacks NMOS and PMOS vertically to continue area scaling and improving the energy efficiency of logic technology. In this study, we report successful CMOS operations of 3DSFET by implementing vertical integration of a Source/Drain (SD), metal gate, and contacts including Self-Aligned Direct Backside Contact (SA-DBC) in an industry-compatible Contacted Poly Pitch (CPP) of 48 nm. |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
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