| Autor: |
Patil, Sharvil, Ganesan, Asha, Shibata, Hajime, Kozlov, Victor, Taylor, Gerry, Shrestha, Prawal, Li, Zhao, Lulec, Zeynep, Vasilakopoulos, Konstantinos, Theertham, Raviteja, Paterson, Donald, Yu, Qingnan, Chowdhury, Aseer |
| Zdroj: |
IEEE Journal of Solid-State Circuits; December 2024, Vol. 59 Issue: 12 p4225-4236, 12p |
| Abstrakt: |
This paper describes a continuous-time (CT) pipelined analog-to-digital converter (ADC) that represents a technology push along both—third-order distortion and noise—dimensions. Distortion is tackled using on-chip digital cancellation of static and timing digital-to-analog converter (DAC) mismatch errors. Low noise is achieved with design choices such as a resistive sub-DAC; a high-precision, on-chip, background-calibrated digital reconstruction filter (DRF); and a tunable LC lattice delay that allows a programmable sampling frequency. Implemented in a 16-nm FinFET process, the 6.4-GS/s prototype achieves an IM3 of −90 dBFS and a small-signal NSD of −164 dBFS/Hz over a 700-MHz bandwidth, while dissipating 703-mW power. Such performance makes it suitable for high-performance instrumentation and communications that demand robustness to large interferers while digitizing small signals. |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
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