| Autor: |
Pradhan, Little, Varma, Renuka, Kshirsagar, Abhijit, Venkatramanan, D., Benedetto, Marco di, Lidozzi, Alessandro |
| Zdroj: |
IEEE Transactions on Industrial Electronics; December 2024, Vol. 71 Issue: 12 p15904-15913, 10p |
| Abstrakt: |
In a cascaded H-bridge (CHB) multilevel inverter, carrier-based pulse width modulation (PWM) schemes are preferred due to ease of computation and implementation. The commonly used level-shifted carrier PWM (LSPWM) introduces extreme disparity in power handled by each module, specifically for CHBs fed by multiple isolated converters from a common dc link. This power imbalance creates asymmetric thermal and electrical stresses leading to premature failures in overstressed modules. One computationally simple solution to this problem is known as first-in-first-out (FIFO) carrier reassignment, which somewhat reduces the power disparity between the modules compared to LSPWM. This article presents a novel carrier-reassignment scheme for nine-level CHB inverters to achieve perfect power balance across the modules. A quadrant-by-quadrant carrier-reassignment scheme is used which results in minimal computational burden. Since the proposed scheme only requires a sampled voltage reference, it can be well integrated into existing inverter control schemes such as dq-control in grid-tied operation. The proposed scheme is first simulated to verify the improved module power balance in a grid-tied configuration. The results are further verified with a hardware prototype operating in grid-connected mode, demonstrating a near-perfect power balance among the modules. |
| Databáze: |
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