Venus Surface Environmental Chamber Test of SiC JFET-R Multi-Chip Circuit Board

Autor: Neudeck, Philip G., Chen, Liang Yu, Greer, Lawrence C., Spry, David J., Prokop, Norman F., Lukco, Dorothy, Krasowski, Michael J., Hunter, Gary W.
Zdroj: Diffusion and Defect Data Part B: Solid State Phenomena; August 2024, Vol. 358 Issue: 1 p7-12, 6p
Abstrakt: This paper describes a first attempt to build and operate a multi-chip prototype lander control and sensor signal digitization electronics circuit board comprised of ten NASA Glenn IC Generation 11 SiC JFET-R IC chips in 460 °C, 9.4 MPa harsh Venus surface conditions. The lander circuit ceased electrical operation prematurely at 107 °C as the Venus chamber heated up. Microscopic post-test inspections indicate that only one of the ten SiC chips on the board failed. Most of circuit-damaging cracks observed on the failed chip corresponded to micron-scale irregularly-shaped dielectric film hillock defects. The study of these defects suggests minor processing changes to eliminate this suspected root failure cause.
Databáze: Supplemental Index