| Autor: |
Watson, Robert N. M., Chisnall, David, Clarke, Jessica, Davis, Brooks, Filardo, Nathaniel Wesley, Laurie, Ben, Moore, Simon W., Neumann, Peter G., Richardson, Alexander, Sewell, Peter, Witaszczyk, Konrad, Woodruff, Jonathan |
| Zdroj: |
IEEE Security & Privacy; 2024, Vol. 22 Issue: 4 p50-61, 12p |
| Abstrakt: |
The memory-safe Capability Hardware Enhanced RISC Instructions (CHERI) C and C++ languages build on architectural capabilities in the CHERI protection model. With the development of two industrial CHERI-enabled processors, Arm’s Morello and Microsoft’s CHERIoT, CHERI may offer the fastest path to widely deployed memory safety. |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
|
