| Autor: |
Park, Hyungjun, Kim, Byung-In, Choi, Dong Gu, Kyu Kim, Hyun, Wook Kang, Tae, Jung Lee, You |
| Zdroj: |
Components, Packaging, and Manufacturing Technology, IEEE Transactions on; 2024, Vol. 14 Issue: 6 p993-1006, 14p |
| Abstrakt: |
The advancement of 2.5-D integration technology has proven to be an efficient means of combining heterogeneous chiplets to achieve advanced design objectives. In the context of 2.5-D integration, especially in high-frequency systems, minimizing timing skew among multiple nets has become imperative. Considering this, the deviation of the wirelength for numerous nets must be constrained within tight bounds to ensure the optimal performance of 2.5-D systems. The interposer used in 2.5-D integration offers enhanced flexibility in octagonal wire routability and interlayer transitions; however, it introduces the challenge of minimizing routing bends to enhance both manufacturability and signal integrity. In our study, we first addressed an interposer routing problem, minimizing both wirelength and bends in octagonal routable interposer design, while adhering to constraints on the length-deviation limits among multiple nets. We formulated a mixed-integer linear programming (MILP) model by considering the requirements of the routing problem. However, the model has several challenges, and the routing problem is NP-hard, indicating that no exact polynomial time method may exist. Consequently, we proposed an efficient routing algorithm that utilizes an assignment heuristic and bidirectional shortest path merge technique. Our algorithm provides a near-optimal solution in terms of the total wirelength and number of bends within an acceptable computation time. As a result, a design task that would have taken a month to complete was finished in less than two days. Experiments on real-world test cases verified that the proposed algorithm consistently delivers satisfactory solutions. |
| Databáze: |
Supplemental Index |
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