| Autor: |
Liang, Honggang, Yu, Yong, Li, Zhixuan, Li, Yuke, Shao, Feng, Zhu, Jingfei, Lu, Yanan, Liang, Jing, Ba, Lansong, Yang, Nan, Li, Yongjie, Peng, Xu, Lu, Yongchun, Kang, Bryan, Wang, Guilei, Zhao, Chao |
| Zdroj: |
IEEE Transactions on Electron Devices; 2024, Vol. 71 Issue: 7 p4132-4137, 6p |
| Abstrakt: |
The 4F2 cell architecture dynamic random access memory (DRAM) has emerged as a candidate for high-density future DRAM, meeting performance, power, area, and cost (PPAC) targets. This study proposes an improved parasitic capacitance-predictively aware design technology co-optimization (DTCO) flow that optimizes the bitline (BL) capacitance from structure and process perspectives, emphasizing manufacturability and scalability. A novel BL process flow is developed to optimize BL capacitance with scalability, utilizing a high-accuracy 3-D field solver for parasitic capacitance extraction of the vertical channel transistor (VCT) array. When air gap is used as the novel BL spacer, the BL capacitance decreases by 49.5%. In addition, we investigate and optimize the PPAC of the DRAM one transistor and one capacitor (1T1C) cell. The novel BL of 4F2 VCT-based 1T1C DRAM demonstrates a 66.6% reduction in BL dynamic power consumption during read/write operations, with 9.4% and 11.6% enhancement in read speed when reading data “1” and “0,” respectively. Moreover, a 58.8% reduction in cell array area and lower costs is yielded compared with the current VCT. |
| Databáze: |
Supplemental Index |
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