| Autor: |
Yue, Jinshan, Liu, Yongpan, Feng, Xiaoyu, He, Yifan, Wang, Jingyu, Yuan, Zhe, Zhan, Mingtao, Liu, Jiaxin, Su, Jian-Wei, Chung, Yen-Lin, Wu, Ping-Chun, Hong, Li-Yang, Chang, Meng-Fan, Sun, Nan, Dou, Chunmeng, Li, Xueqing, Liu, Ming, Yang, Huazhong |
| Zdroj: |
IEEE Journal of Solid-State Circuits; 2024, Vol. 59 Issue: 5 p1612-1627, 16p |
| Abstrakt: |
Computing-in-memory (CIM) chips have demonstrated the potential high energy efficiency for low-power neural network (NN) processors. Even with energy-efficient CIM macros, the existing system-level CIM chips still lack deep exploration on sparsity and large models, which prevents a higher system energy efficiency. This work presents a CIM NN processor with more sufficient support of sparsity and higher utilization rate. Three key innovations are proposed. First, a set-associate blockwise sparsity strategy is designed, which simultaneously saves execution time, power, and storage space. Second, a ping-pong weight update mechanism is proposed for a higher utilization rate, enabling simultaneous execution of CIM and write operations. Third, an efficient CIM macro is implemented with adaptive analog-digital converter (ADC) precision for better sparsity utilization and performance-accuracy trade-off. The 65-nm fabricated chip shows 9.5-TOPS/W system energy efficiency at 4-bit precision, with 6.25 $\times $ actual improvement compared with a state-of-the-art CIM chip. Besides, this work supports high CIM execution accuracy on the ImageNet dataset. |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
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