| Autor: |
Mittal, Rishabh, Shibata, Hajime, Patil, Sharvil, Krommenhoek, Erik, Shrestha, Prawal, Manganaro, Gabriele, Chandrakasan, Anantha P., Lee, Hae-Seung |
| Zdroj: |
IEEE Journal of Solid-State Circuits; 2024, Vol. 59 Issue: 4 p1158-1170, 13p |
| Abstrakt: |
We introduce a continuous-time (CT) pipeline analog-to-digital converter (ADC) featuring a time-interleaved sub-ADC-digital-to-analog converter (DAC) path in its first stage. The proposed sub-ADC-DAC path enhances the ADC’s bandwidth by improving the signal cancellation at the summing node of the first stage. In addition, we have developed an inductorless delay line for the first stage, improving the amplitude and phase matching, thus minimizing the input signal leakage into the backend ADC. Furthermore, the theoretical jitter limitations in the CT pipeline architecture have been explored, and the proposed theory is compared against the measured results. The prototype ADC was fabricated in a 16-nm FinFET process. The ADC achieves a peak signal-to-noise ratio (SNR) of 61.7 dB at low frequencies and 60.8 dB at high frequencies across a 1-GHz bandwidth. The active area of the ADC is 0.77 mm2, and it consumes 240 mW. The Schreier figure of merit (FOM $_{S}$ ) is 157.9 dB, which is amongst the best for CT ADCs with bandwidth greater than 500 MHz. |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
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