| Autor: |
Ye, Zonglin, Geng, Xinlin, Xiao, Yao, Xie, Qian, Wang, Zheng |
| Zdroj: |
IEEE Journal of Solid-State Circuits; 2024, Vol. 59 Issue: 3 p677-689, 13p |
| Abstrakt: |
A 24–28-GHz sub-50-fsrms jitter fractional- $N$ charge pump phase-locked loop (CPPLL) is presented in this work. A dual-digital-to-time converter (DTC)-assisted time-amplifying phase-frequency detector (TAPFD) structure is proposed to suppress the in-band noise of charge pump (CP) and cancel the quantization error (QE) simultaneously while keeping low power consumption. Moreover, a cascadable DTC gear estimation and nonlinearity compensation algorithm (NLC) is also proposed to mitigate the fractional spur. The presented PLL achieves a measured integrated rms jitter including spurs of 37.1 fs with −255.2-dB FoM $_{J}$ for integer- $N$ channel and 45.6 fs with −253.0-dB FoM $_{J}$ for fractional- $N$ channel. |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
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