Design of high speed hybrid full adder using reversible logic gates
| Autor: | Bhookya, R. V. Prasad, Ravindra, J. V. R. |
|---|---|
| Zdroj: | AIP Conference Proceedings Online; February 2024, Vol. 2942 Issue: 1 p020017-20024, 8p |
| Databáze: | Supplemental Index |
| Externí odkaz: |
|