| Autor: |
Lee, Myungguk, Cho, Jaeik, Choi, Junung, Choi, Won Joon, Lee, Jiyun, Jang, Iksu, Moon, Changjae, Kim, Gain, Kim, Byungsub |
| Zdroj: |
Circuits and Systems I: Regular Papers, IEEE Transactions on; January 2024, Vol. 71 Issue: 1 p373-382, 10p |
| Abstrakt: |
This paper presents compact single-ended wireline transceivers with software-generated receiver front-ends. The developed software framework significantly shortens the physical design time of 1/N-rate wireline receiver front-ends. The physical layouts of various receiver front-ends were software-generated in four different CMOS technology nodes (28 nm, 40 nm, 65 nm, and 90 nm) with four different front-end architectures targeting various data rates. In the post-layout simulation, the receiver front-ends generated within a second by the software achieved nearly the same performances as the manually-designed receiver front-ends that require more than about 30 hours of design time. For demonstration, we generated 8 Gb/s full-rate, 10 Gb/s half-rate, 12 Gb/s, and 20 Gb/s quarter-rate receiver front-ends, and fabricated them with a manually-designed feed-forward equalization transmitter in 28 nm CMOS process. The transceivers were measured with the data rate up to 20 Gb/s while consuming 1.39 pJ/b at the channel loss of −9.2 dB. The transceiver with software-generated receiver achieved the highest data rate per area as well as the smallest area among the relevant prior arts while reducing the physical design time of the receiver front-end by more than 140,000 times. |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
|
