| Autor: |
Kim, Sangjin, Li, Zhiyong, Um, Soyeon, Jo, Wooyoung, Ha, Sangwoo, Lee, Juhyoung, Kim, Sangyeob, Han, Donghyeon, Yoo, Hoi-Jun |
| Zdroj: |
IEEE Journal of Solid-State Circuits; January 2024, Vol. 59 Issue: 1 p102-115, 14p |
| Abstrakt: |
This article presents DynaPlasia, a reconfigurable eDRAM-based in- memory computing (IMC) processor with a novel triple-mode cell. It enables higher system-level performance and efficiency in a resource-limited environment. DynaPlasia proposes five key features that can enhance the energy efficiency and area efficiency of the IMC accelerator: 1) dynamic reconfigurable core architecture (DRECA), which dynamically reconfigures the effective IMC macro size according to DNN workloads; 2) the triple-mode cell is reconfigured as IMC PE, unit DAC, and unit cell to optimize system resource utilization adaptively; 3) hierarchical in- memory ADC (Hi-ADC) reduces ADC area overhead with tripe-mode cell and saves power with the hierarchical operation; 4) signed-input signed-weight (SISW) IMC reduces logic switching activity with signed magnitude representation; and 5) leakage-tolerant computing (LTC) to enable high-density cell design. The DynaPlasia is fabricated in 28-nm CMOS technology and occupies a 20.25-mm 2 die area with 9.6-Mb cell capacity. Its measured system peak throughput is 19.5 TOPS (4 b–5 b), and system peak efficiency is 56.0 TOPS/W (4 b–5 b). Even with the ResNet50 @ ImageNet dataset, system efficiency is 29.5 TOPS/W which is 2.5 $\times $ higher than the previous state-of-the-art. |
| Databáze: |
Supplemental Index |
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