| Autor: |
Rathaur, Shivendra K., Wu, Jui-Sheng, Yang, Tsung-Ying, Amin, Asifa, Dixit, Abhisek, Chang, Edward Yi |
| Zdroj: |
IEEE Transactions on Electron Devices; September 2023, Vol. 70 Issue: 9 p4584-4590, 7p |
| Abstrakt: |
This article investigates a hybrid ferroelectric charge trap (HFCT)-based HfZrO4/HfOXNY/ Al2O3/AlGaN/GaN gate-stack under constant positive gate voltage stress over time and temperature variability. The experimentally characterized breakdown (BD) analysis implies a thermally assisted tunneling (TAT) BD owing to the negative temperature coefficient of BD voltage. Moreover, the step gate stress depicts a relatively lower BD voltage of ~20 V compared to the linear gate stress voltage of ~21.85 V attributed to performance degradation due to stress. In addition, the Weibull distribution, which validates the intrinsic degradation of the gate-stack, is used to estimate its lifetime. An operating voltage of ~7.41 V exhibits a ten-year lifetime at 150 °C extrapolated over multiple stress conditions. Furthermore, the activation energy from ~0.63 to ~0.67 eV validates deep-level E3 traps within the GaN barrier layer and the trapping of electrons during degradation, thus, revealing the point-level defect generation leading to the time-dependent gate dielectric BD (TDDB). The robustness and superior reliability of the HFCT gate-stack are recognized, and the single degradation mechanism contributes to the final device failure in the TDDB test. |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
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