| Autor: |
Park, Kyu-Sang, Khashaba, Amr, Abdelrahman, Ahmed, Li, Yongxin, Wang, Tianyu, Xia, Ruhao, Pal, Nilanjan, Hanumolu, Pavan Kumar |
| Zdroj: |
IEEE Journal of Solid-State Circuits; 2023, Vol. 58 Issue: 7 p2064-2074, 11p |
| Abstrakt: |
This article presents techniques to improve the frequency stability of $RC$ oscillators by performing first- and second-order temperature compensation without needing resistors with opposite temperature coefficients (TCs). Using the proposed three-point digital trim, a prototype 100-MHz frequency-locked loop (FLL)-based $RC$ oscillator fabricated in a 65-nm CMOS process achieves an inaccuracy of ±140 ppm over −40 °C to 95 °C, 83-ppm/V voltage sensitivity, 1.3-ppm Allan deviation floor, and 1- $\mu \text{W}$ /MHz power efficiency. When only a single-point trim is performed using a multiple linear regression model leveraging the strong correlation between three switched resistors, the frequency inaccuracy is ±587 ppm. |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
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