| Autor: |
Vanderpool, Brian, Restle, Phillip J., Fluhr, Eric, Still, Gregory, Campisano, Francesco A., Charmichael, Ian, Marz, Eric, Batra, Rahul, Willaman, Richard |
| Zdroj: |
IEEE Journal of Solid-State Circuits; January 2023, Vol. 58 Issue: 1 p102-110, 9p |
| Abstrakt: |
Digital droop sensors (DDSs) with core throttling mitigate microprocessor voltage droops and enable a voltage control loop (undervolting) to offset loadline uplift plus noise effects, protecting reliability $V_{\mathrm {DDMAX}}$ . These combine with a runtime algorithm for workload optimized frequency (WOF) that deterministically maximizes core frequency. The combined effect is demonstrated across a range of workloads, including SPEC, and provides up to a 15% frequency boost and a 10% reduction in core voltage. |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
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