Autor: |
Huang, Chi-Hsiang, Mandal, Arindam, Pena-Colaiocco, Diego, Silva, Edevaldo Pereira Da, Sathe, Visvesh S. |
Zdroj: |
IEEE Journal of Solid-State Circuits; January 2023, Vol. 58 Issue: 1 p68-77, 10p |
Abstrakt: |
The system on chip (SoC) domains in wearable and Internet-of-Things (IoT) applications are frequently duty-cycled, placed in a power-gated (Sleep) mode, and woken up for brief periods to perform tasks (Active mode). Duty cycling reduces steady-state leakage energy loss, but the significant quantity of energy stored in the domain decoupling capacitor ( $C_{O}$ ) at the onset of Sleep mode is discharged through domain leakage. This energy overhead significantly degrades overall system efficiency. This article presents an architecture that efficiently reverses power flow in a buck converter at the onset of Sleep to recycle the stored energy stored in $C_{O}$ before Sleep, thus minimizing transient Sleep leakage losses ( $E_{\mathrm{ loss}}$ ). A fully digital run-time $E_{\mathrm{ loss}}$ optimizer is presented to achieve optimal recycling and demonstrated in a voltage domain consisting of a duty-cycled, buck-regulated ARM M0 processor. Measurements indicate that 59.4% $E_{\mathrm{ loss}}$ reduction is achieved with 3.2-ms Sleep duration. These savings translate to total system energy savings of 56.6% for a duty-cycled processor executing 5k cycles during the Active operation. |
Databáze: |
Supplemental Index |
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