| Autor: |
Nishii, Katsunori, Nishitsuji, Mitsuru, Yokoyama, Takahiro, Yamamoto, Shinji, Tamura, Akiyoshi, Inoue, Kaoru |
| Zdroj: |
Japanese Journal of Applied Physics; April 1999, Vol. 38 Issue: 4 p2555-2555, 1p |
| Abstrakt: |
High-current and high-transconductance self-aligned p+-GaAs junction HFETs (PJ-HFETs) of a complete enhancement-mode operation have been developed for the first time. Due to the advantages of the p/n junction, the barrier height of 1.12 eV has been obtained. To obtain high activation for the Si implanted epitaxial layers, we optimized the annealing conditions. The 0.8 µm-gate complete enhancement mode PJ-HFET with a large forward gate voltage swing of more than 1.5 V exhibited a K-value of 400 mS/Vmm, a maximum transconductance (gmMAX) of 410 mS/mm and a maximum drain current (IMAX) of 380 mA/mm with a threshold voltage (Vth) of 0.2 V. The standard deviation of Vthwas 18.4 mV across a 3 inch wafer. Operated with a drain bias of 3.3 V, the PJ-HFET demonstrated a power-added efficiency (PAE) of 39.5% with an adjacent channel leakage ratio (ACPR) of -57.4 dBc at an output power (Pout) of 21.5 dBm and a frequency of 1.9 GHz. |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
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