| Autor: |
Kiyoshi Arita, Kiyoshi Arita, Masashi Akamatsu, Masashi Akamatsu, Tanemasa Asano, Tanemasa Asano |
| Zdroj: |
Japanese Journal of Applied Physics; March 1998, Vol. 37 Issue: 3 p1278-1278, 1p |
| Abstrakt: |
Plasma-process induced degradation of gate oxide of metal/oxide/silicon (MOS) devices on silicon-on-insulator (SOI) structures and bulk wafers was investigated. In order to evaluate the degradation of the gate oxide, the charge-to-breakdown Qbdof the MOS capacitors was measured under a constant current condition. It was found that the degradation of the gate oxide could be drastically suppressed using SOI. A thicker buried oxide layer showed greater suppression of the gate oxide degradation. A smaller device island size showed lower gate oxide degradation, although the dependence was rather weak. An electrical model is discussed, to account for the effect of SOI, in which the capacitance of the buried oxide played a key role in suppressing the degradation. |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
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