| Autor: |
Kazuko Yamamoto, Kazuko Yamamoto, Taiga Uno, Taiga Uno, Kiyomi Koyama, Kiyomi Koyama |
| Zdroj: |
Japanese Journal of Applied Physics; December 1997, Vol. 36 Issue: 12 p7499-7499, 1p |
| Abstrakt: |
The hierarchical processing of Levenson-type phase shifter generation has been developed. It is integrated with a computer aided design (CAD) system, which makes modification of conflict spots easy for designers. In order to keep CAD data compressed during phase assignment, phase information is stored as a combination of two properties, phase and group reversal. Phase assignment is generally executed cell-by-cell from the bottom up. In each cell, the region processed is kept to a minimum in order to achieve efficient processing. The intrinsic problem of bottom-up hierarchical processing is the merge problem in which patterns to be merged at the cell boundary have different phases, and it is treated with retry processing. The hierarchical phase assignment was applied to 4M-bit memory with a core circuit and the effectiveness of the hierarchical processing was demonstrated. The processed data were compressed to about 1/20, and processing time was reduced by at least 1/2 of those by flat processing. |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
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