| Autor: |
Kiyoshi Arita, Kiyoshi Arita, Masashi Akamatsu, Masashi Akamatsu, Tanemasa Asano, Tanemasa Asano |
| Zdroj: |
Japanese Journal of Applied Physics; March 1997, Vol. 36 Issue: 3 p1505-1505, 1p |
| Abstrakt: |
The charge build-up of silicon-on-insulator (SOI) structures during reactive ion etching has been investigated. The charge build-up was evaluated by using metal/nitride/oxide/silicon (MNOS) capacitors fabricated on SOI. It has been found that the charge build-up can be drastically reduced by using SOI, while the reduction in etching rate is only 3% less than that attained using bulk Si wafers at a relatively high RF power condition. The amount of charge build-up has been found to decrease the thickness of the buried oxide layer increases. A model to explain these phenomena is discussed. |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
|
