| Autor: |
Young, Chadwin D., Bersuker, Gennadi, Heh, Dawei, Neugroschel, Arnost, Choi, Rino, Yong, Chang, Tun, Joey, Hun, Byoung |
| Zdroj: |
ECS Transactions; September 2007, Vol. 11 Issue: 4 p335-346, 12p |
| Abstrakt: |
Various conventional and novel electrical characterization techniques have been combined with comprehensive analysis to properly evaluate high-k gate dielectric stack structures. These measurement methodologies and analysis techniques are intended to separate contribution from the pre-existing defects, which may serve as charge traps, from the stress-generated defects. In addition, the differentiation of electrically active bulk high-k traps and interfacial layer traps has been demonstrated. |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
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