| Autor: |
Lim, JongHeun, Yoon, BoUn, Kim, KyungHyun, and, YoungSun Ko, Kang, ChangJin |
| Zdroj: |
ECS Transactions; October 2010, Vol. 33 Issue: 10 p153-156, 4p |
| Abstrakt: |
This paper deals with chemical mechanical planarization (CMP) technology to develop 3D (3-Dimentional) stacked Flash Memory. The purpose of IGD CMP in full wafer process is to recover local planarity and surface roughness. Based on small elastic deflection theory, the following formula is derived. CMP Step Height of local planarity H = 3.5x(Wxg/4)1/2 x { 0.75x(1-n2)/E + 0.75x(1-n2)/E }1/2 . When this formula is applied, local planarity H should be under 30A, which is confirmed through the experiment. Channel Silicon CMP is the important planarization process to improve the single crystal silicon property. The polished Channel Silicon layer has surface roughness of about 1A rms using colloidal silica based slurry with self stop function. |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
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