(Invited) Evaluation of Stacked Nanowires Transistors for CMOS: Performance and Technology Opportunities

Autor: Gaben, Loic, Barraud, Sylvain, Samson, Pierre, Jaud, Anne, Martinie, Sebastien, Rozeau, Olivier, Lacord, Joris, Arvet, Christian, Vizioz, Christian, Bustos, Jessy, Dallery, Alexandre, Pauliac, Sebastien, Balan, Viorel, Euvrard, Catherine, Perrot, Cedric, Loup, Virginie, Besson, Pascal, Hartmann, Michel, Monfray, Stephane, Boeuf, Frederic, Skotnicki, Thomas, Balestra, Francis, Vinet, Maud
Zdroj: ECS Transactions; May 2016, Vol. 72 Issue: 4 p43-54, 12p
Abstrakt: Stacked-NW FETs pave the way for significant increase in device effective width over FinFET and FDSOI. An increase of performance and/or a decrease of device footprint is expected by using thin and wide NW channels also known as nanosheets or nanoplates. This paper points out Gate Last integration issues of stacked-NWs. Two solutions labeled as NW First and NW Last are presented featuring internal spacer formation. A demonstration of self-aligned gate and spacers is proposed, involving Hydrogen Silsesquioxane (HSQ) lithography through silicon channels.
Databáze: Supplemental Index