| Abstrakt: |
The reliability issues are major concern in safety, mission, and business-critical applications such as Aircraft flight control, Aerospace applications, Defense communications, Bank transactions, etc. There will be immense loss if these systems do not operate in the field, i.e. in real time. The responsibility of designers and engineers is to build highly reliable intelligent systems by adding redundancy like hardware, software, information and time. To raise the reliability of the system, the hardware redundancy is used in this study. In the era of microelectronics reliability, the triple modular redundancy (TMR) configuration is the most common technique used to mitigate one single event upset (SEU) error. This work mainly focuses on majority voting of quintuple modular redundancy (QMR) system to tolerate two SEU errors for the betterment of reliability. Three proposed majority voters of QMR or 5-MR configurations were discussed, analyzed and implemented in this study. Simulation results show that the first proposed 5-MR design offers a better figure-of-merit (FOM-52.55), a lower delay (0.390 ns) and lower power dissipation (367.8 µm2) than others. The lower power dissipation (7.633 µW) is achieved by the second proposed method with good FOM (48). Also, three application examples, namely logical AND, synthetic highs and image fusion are implemented on Altera FPGA EP4CE115F29C7 device using Quartus II synthesis tool using the proposed Q-MR configuration approaches. Simulation results show that the proposed methods offer better results than the existing method. |
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