| Autor: |
Yu, Qun Xiu, Zhang, Shou Ming, Wang, Chao, Xie, Li Zhi |
| Zdroj: |
Applied Mechanics and Materials; February 2015, Vol. 734 Issue: 1 p621-624, 4p |
| Abstrakt: |
In this paper the digital watermarking algorithm deep into the field of integrated circuits combined with the JPEG image watermarking processes and SOPC technology, Verilog HDL language is used to design and implement of a reusable JPEG decoder IP core which can be embedded, realizing the JPEG decoding on FPGA platform and further completing the watermark embedding. The JPEG decoder is tested through the Modalism simulation software and would be revised until the simulation results become correct. Finally, the Altera development board EP2C70F896C6N of CycloneII series is used to complete the system design. The results prove that the system can run well, the program which can obtain a larger increase speed in exchange for consuming a little hardware resource does work. |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
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