| Autor: |
Sun, Weifeng, Xie, Liang, Jia, Kan, Zhou, Yangfan, Qian, Qingsong, Shi, Longxing |
| Zdroj: |
IETE Journal of Research; November 2011, Vol. 57 Issue: 6 p550-556, 7p |
| Abstrakt: |
AbstractA 320 × 256 readout integrated circuit (ROIC) for infrared focal plane arrays is designed and fabricated with 0.5 μm n-well Complementary Metal Oxide Semiconductor (CMOS) process. A sub-circuit Simulation Program with Integrated Circuit Emphasis (SPICE) model of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) for low-temperature simulation is also presented and has been applied in the ROIC design. An auto-bias capacitor transimpedance amplifier pixel structure with selectable input gain is used to prevent pixel crosstalk and accommodate the dynamic range requirements. A shared buffer and dynamic tail current technology are applied in the column readout stage to reduce the power consumption. A fast-settling, low static power, high-linearity output buffer have also been suggested. The experimental chip of the proposed ROIC has been measured at 77 K. Under the power supply of 5.5 V, it has a power dissipation of 78.3 mW. The linearity is above 99%. The ROIC can operate at 110 frames/s when the clock is 10 MHz. The measured results also verify the validity of the low-temperature SPICE model of MOSFET. |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
|
