Simulation, synthesis, and verification of pipelined asynchronous VLSI circuits
| Autor: | Furey, D |
|---|---|
| Zdroj: | Computer Standards & Interfaces; 1999, Vol. 20 Issue: 6-7 p473-473, 1p |
| Databáze: | Supplemental Index |
| Externí odkaz: |
|
| Autor: | Furey, D |
|---|---|
| Zdroj: | Computer Standards & Interfaces; 1999, Vol. 20 Issue: 6-7 p473-473, 1p |
| Databáze: | Supplemental Index |
| Externí odkaz: |
|
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