| Autor: |
Patnaika, Santosh Kumar, Banerjee, Swapna |
| Zdroj: |
Procedia Engineering; May2012, Vol. 30, p210-217, 8p |
| Abstrakt: |
In a high speed latched comparator the minimum amount of differential voltage at the input can be detected correctly at the output of the comparator if it does not get affected by the noises and errors generated inside the comparator. To improve the performance of the latched comparator, all the noises and errors should be minimized. In this paper, an attempt has been made to reduce the noises and errors generated within the latched comparator by introducing extra circuit elements. The noise and error optimized comparator shows an improvement in the effective resolution from 7.46-bit to 8.3-bit. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
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