| Autor: |
Kalavathidevi, T., Venkatesh, C. |
| Zdroj: |
Computer Science & Telecommunications; 2012, Vol. 34 Issue 2, p3-16, 14p, 15 Diagrams, 3 Charts, 4 Graphs |
| Abstrakt: |
In modern communication systems, reducing power consumption has become a fundamental design goal, especially for VLSI integrated circuits used in mobile communication systems. Asynchronous design is progressively becoming more an attractive alternative to synchronous design because of its potential for high-speed and low-power. Asynchronous circuits will therefore generally dissipate less power than synchronous ones. The proposed method is focused on the design of VLSI architecture for a Viterbi Decoder by using low power VLSI design techniques at circuit level with asynchronous self timed control and Differential Cascode Voltage Switch Logic (DCVSL). The asynchronous designs based on Pre Charged Half buffer (PCHB) templates. The asynchronous Viterbi decoder comprises of BMU, PMU and a SMU. Communication within the decoder blocks are controlled by the Request-Acknowledge handshake pair which respectively signals that valid data is ready and that it has been accepted. The design of various units of Viterbi Decoder is done by using T - SPICE in TSMC 0.25um technology. The simulation results shows 90% power reduction has been achieved by using asynchronous design technique compared to that of the synchronous design. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Supplemental Index |
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