| Autor: |
Sobh, Tarek, Elleithy, Khaled, Mahmood, Ausif, Karim, Mohammed, Vasiliadis, D. C., Rizos, G. E., Vassilakis, C. |
| Zdroj: |
Innovative Algorithms & Techniques in Automation, Industrial Electronics & Telecommunications; 2007, p107-111, 5p |
| Abstrakt: |
Banyan Networks are a major class of Multistage Interconnection Networks (MINs). They have been widely used as efficient interconnection structures for parallel computer systems, as well as switching nodes for high-speed communication networks. Their performance is mainly determined by their communication throughput and their mean packet delay. In this paper we use a performance estimation model that is based on a universal performance factor, which includes the importance aspect of each of the above individual performance factors (throughput and delay) in the design process of a MIN. The model can also uniformly be applied to several representative networks. The complexity of the model requires to be investigated by time-consuming simulations. In this paper we study a typical (8X8) Baseline Banyan Switch that consists of (2X2) Switching Elements (SEs). The objective of this simulation is to determine the optimal buffer size for the MIN stages under different conditions [ABSTRACT FROM AUTHOR] |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
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