| Autor: |
Rao, Josyula R., Sunar, Berk, Kerins, T., Marnane, W. P., Popovici, E. M., Barreto, P. S. L. M. |
| Zdroj: |
Cryptographic Hardware & Embedded Systems - CHES 2005; 2005, p412-426, 15p |
| Abstrakt: |
In this paper the benefits of implementation of the Tate pairing computation on dedicated hardware are discussed. The main observation lies in the fact that arithmetic architectures in the extension field GF(36m) are good candidates for parallelization, leading to a similar calculation time in hardware as for operations over the base field GF(3m). Using this approach, an architecture for the hardware implementation of the Tate pairing calculation based on a modified Duursma-Lee algorithm is proposed. Keywords: Tate pairing, hardware accelerator, characteristic three, tower fields. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
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