| Autor: |
Poczekajło, Paweł, Gołka, Łukasz, Suszyński, Robert, Widuliński, Patryk |
| Předmět: |
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| Zdroj: |
Procedia Computer Science; 2024, Vol. 246, p2400-2409, 10p |
| Abstrakt: |
The article concerns the issue of multicore processing and implementation. The topic is introduced considering the functional division of various architectures. Examples of large-scale multicore architectures (with 144 and 1024 computational cores) are also presented. The main goal of the authors is to present the concept of implementing a multicore architecture in a Field-programmable gate array (FPGA). An available solution of the Nios II processor from the Intel library in the Quartus environment is presented. Additionally, the authors discuss their own concept of a computational core, outlining key assumptions, advantages and disadvantages, as well as potential issues. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Supplemental Index |
| Externí odkaz: |
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